In the field of semiconductor devices, the device density is increasing while the device dimensions are continuously reduced. The demand on packaging and interconnecting techniques in such high density devices is also complicated by mechanical fragility and manufacturing yield issues. Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps. The function of chip package includes power distribution, signal distribution, heat dissipation, protection and support, and so on. As a semiconductor become more complicated, the traditional package techniques, such as lead frame package, flex package, rigid package technique, can't support the demand of producing smaller chip packages with high density elements in the package.
Conventional package technologies have to divide a wafer into respective dies, mount the die on a support structure, and wire the die to the support structure by a wire bonding process. These techniques are time consuming and subject to defects created during the manufacturing process. Since chip packaging techniques are highly influenced by the development of integrated circuits, there is a constant demand to enhance the packaging processes to provide more efficient and robust integrated circuit packages.
The trend of package technologies is toward ball grid array (BGA), flip chip (FC-BGA), chip scale package (CSP), Wafer level package (WLP) to meet the efficiency and reliability requirements. “Wafer level package” is to be understood to mean that the entire package and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) of the semiconductor wafer into packaged chips. Generally, after completion of all packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dice. The wafer level package has extremely small dimensions combined with extremely good electrical properties, making it a popular technology for advanced packaging.
Because the wafer level package technique utilizes the whole wafer as one object, before performing a scribing/dicing process, all of the packaging and testing would have already been accomplished. Furthermore, with the wafer level package technique the processes of wire bonding, die mount, molding and/or under-fill may be omitted. The omission of these more mechanical process steps can reduce the amount of defects introduced by positioning errors or mechanical reliability. By utilizing wafer level package technique, the cost and manufacturing time can be reduced, and the package reliability can be enhanced.
Though the advantages of wafer level package technique mentioned above are significant, some issues still exist that hinder the acceptance of wafer level package technique. For instance, the coefficient of thermal expansion (CTE) mismatch between the materials of a wafer level package and the mother board (PCB) becomes another critical factor to mechanical instability of the structure. The total number of interconnects may be limited by the chip size area with no way to provide multi-chip and system in package solutions.
Thus, a need still remains for an integrated circuit package system with embedded die superstructure, in order to enhance the manufacturing processes and deliver flexible system solutions. In view of the constant demand for increased performance, reliability, and reduced size of the products, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.